8T73S208 Datasheet, Buffer, Integrated Device Technology

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8T73S208 Features and benefits

* One differential input reference clock
* Differential pair can accept the following differential input levels: LVDS, LVPECL, CML
* Integrated .

8T73S208 Application

demanding well-defined performance and repeatability. The integrated input termination resistors make interfacing to the.

8T73S208 Description

The 8T73S208 is a high-performance differential LVPECL clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T73S208 is characterized to operate from a 2.5.

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